1/9 february 2002 n 5v tolerant inputs n high speed: t pd = 4.2ns (max.) at v cc = 3v n power down protection on inputs and outputs n symmetrical output impedance: |i oh | = i ol = 24ma (min) at v cc = 3v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 1.65v to 3.6v (1.2v data retention) n pin and function compatible with 74 series 541 n latch-up performance exceeds 500ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74lvc541a is a low voltage cmos octal bus buffer (3-state) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos tecnology. it is ideal for 1.65 to 3.6 v cc operations and low power and low noise applications. the 3 state control gate operates as two input and such that if either g1 or g2 are high, all eight outputs are in the high impedance state. in order to enhance pc board layout, the 74lvc541a offers a pinout having inputs and outputs on opposite sides of the package. this device is designed to interface directly high speed cmos systems with ttl and nmos components. it has more speed performance at 3.3v than 5v ac/act family, combined with a lower power consumption. all inputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvc541a octal d-type latch high performance this is preliminary information on a new product now in development are or undergoing evaluation. details subject to change wit hout notice. pin connection and iec logic symbols order codes package tube t & r sop 74lvc541am 74lvc541amtr tssop 74LVC541ATTR tssop sop preliminary data
74lvc541a 2/9 input and output equivalent circuit pin description truth table x=dont care; z=high impedance absolute maximum ratings absolute maximum rating are those value beyond which damage to the device may occour. functional operation under these conditio n is not implied 1) i o absolute maximum rating must be observed 2) v o < gnd, v o > v cc pin no symbol name and function 1, 19 g1 , g2 output enable inputs 2, 3, 4, 5, 6, 7, 8, 9 a1 to a8 data inputs 18, 17, 16, 15, 14, 13, 12, 11 y1 to y8 data outputs 10 gnd ground (0v) 20 v cc positive supply voltage input output g1 g2 an yn hxxz xhxz llhh llll symbol parameter2 value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage (v cc = 0v) -0.5 to +7.0 v v o dc output voltage (high or low state) (note 1) -0.5 to v cc + 0.5 v i ik dc input diode current - 50 ma i ok dc output diode current (note 2) - 50 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current per supply pin 100 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c
74lvc541a 3/9 recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2v at v cc = 3.0v dc specification symbol parameter value unit v cc supply voltage (note 1) 1.65 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage (v cc = 0v) 0 to 5.5 v v o output voltage (high or low state) 0 to v cc v i oh , i ol high or low level output current (v cc = 3.0 to 3.6v) 24 ma i oh , i ol high or low level output current (v cc = 2.7 to 3.0v) 12 ma i oh , i ol high or low level output current (v cc = 2.3 to 2.7v) 8ma i oh , i ol high or low level output current (v cc = 1.65 to 2.3v) 4ma t op operating temperqture -40 to 85 c dt/dv input rise and fall time (note 2) 0 to 10 ns/v symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. v ih high level input voltage 1.65 to 1.95 0.65v cc 0.65v cc v 2.3 to 2.7 1.7 1.7 2.7 to 3.6 2 2 v il low level input voltage 1.65 to 1.95 0.35v cc 0.35v cc v 2.3 to 2.7 0.7 0.7 2.7 to 3.6 0.8 0.8 v oh high level ouput voltage 1.65 to 3.6 i o =-100 m av cc -0.2 v cc -0.2 v 1.65 i o =-4 ma 1.2 1.2 2.3 i o =-8 ma 1.7 1.7 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 3.0 i o =-24 ma 2.2 2.2 v ol low level output voltage 1.65 to 3.6 i o =100 m a 0.2 0.2 v 1.65 i o =4 ma 0.45 0.45 2.3 i o =8 ma 0.7 0.7 2.7 i o =12 ma 0.4 0.4 3.0 i o =24 ma 0.55 0.55 i i input leakage current 3.6 v i = 0 to 5.5v 5 5 m a i off power off leakage current 0 v i or v o = 5.5v 100 100 m a i oz high impedance output leakage current 3.6 v i = v ih orv il v o = 0 to 5.5v 5 5 m a i cc quiescent supply current 3.6 v i = v cc or gnd 10 10 m a v i or v o = 3.6 to 5.5v 10 10 d i cc i cc incr. per input 2.7 to 3.6 v ih = v cc -0.6v 500 500 m a
74lvc541a 4/9 dynamic switching characteristics 1) number of output defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining output s is measured in the low state. ac electrical characteristics 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either high or low (t oslh = | t plhm - t plhn |, t oshl = | t phlm - t phln | 2) parameter guaranteed by design capacitance characteristics 1) c pd is defined as the value of the ics internal equivqlent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average current cqn be obtqined by the following equation. i cc(opr) = c pd x v cc x f in + i cc /n (per circuit) symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. v olp dynamic low level quiet out- put (note 1) 3.3 c l = 50pf v il = 0v, v ih = 3.3v 0.8 v v olv -0.8 symbol parameter test condition value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time 1.65 to 1.95 30 1000 2.0 ns 2.3 to 2.7 30 500 2.0 2.7 50 500 2.5 1.5 1.5 3.0 to 3.6 50 500 2.5 1 1 t pzl t pzh output enable time 1.65 to 1.95 30 1000 2.0 ns 2.3 to 2.7 30 500 2.0 2.7 50 500 2.5 1 1 3.0 to 3.6 50 500 2.5 1 1 t plz t phz output disable time 1.65 to 1.95 30 1000 2.0 ns 2.3 to 2.7 30 500 2.0 2.7 50 500 2.5 2 2 3.0 to 3.6 50 500 2.5 2 2 t oslh t oshl output to output skew time (note1, 2) 2.7 to 3.6 1 1 ns symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. c in input capacitance 4pf c pd power dissipation capacitance (note 1) 1.8 f in = 10mhz 28 pf 2.5 30 3.3 34
74lvc541a 5/9 test circuit r t = z out of pulse generator (typically 50 w ) test circuit and waveform symbol value symbol v cc 1.65 to 1.95v 2.3 to 2.7v 2.7v 3.0 to 3.6v c l 30pf 30pf 50pf 50pf r l = r 1 1000 w 500 w 500 w 500 w v s 2 x v cc 2 x v cc 6v 7v v ih v cc v cc 2.7v 3.0v v m v cc /2 v cc /2 1.5v 1.5v v oh v cc v cc 3.0v 3.5v v x v ol + 0.15v v ol + 0.15v v ol + 0.3v v ol + 0.3v v y v oh - 0.15v v oh - 0.15v v oh - 0.3v v oh - 0.3v t r = t r <2.0ns <2.0ns <2.5ns <2.5ns
74lvc541a 6/9 waveform 1: propagation delays, (f=1mhz; 50% duty cycle) waveform 2: output enable and disable times (f=1mhz; 50% duty cycle)
74lvc541a 7/9 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
74lvc541a 8/9 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
74lvc541a 9/9 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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